The present invention relates to a semiconductor device and the manufacturing technology thereof, and relates to a technology that is effective when applied, for example, to a semiconductor device in which an electrode of a semiconductor chip is electrically coupled to a terminal of a wiring substrate via a wire.
In Japanese Patent Laid-Open No. 1986-105851 (Patent Literature 1), there is described a method in which bonding pads provided in two rows in each of two regions facing each other are coupled by wire bonding. In the Patent Literature 1, there is described that, of the bonding pads in two rows, the outside row with respect to the boundary line of respective regions is set to be a first bond and the inside row is set to be a second bond.
There is a technology of electrically coupling a terminal of a wiring substrate to an electrode of a semiconductor chip mounted over the wiring substrate via a wire.
Recently, along with a request for higher functionality of semiconductor devices, the number of the terminals (hereinafter, referred to as terminal number) tends to increase.
However, simple increase in the terminal number results in a larger planar size of the wiring substrate. When each planar size (outside dimension) of a plurality of terminals is made smaller as a countermeasure for this, a margin for stably coupling the wire to the terminal becomes smaller.
The other purposes and the new feature will become clear from the description of the present specification and the accompanying drawings.